1. Field of the Invention
The present invention relates to a configuration of a nonvolatile semiconductor memory which is capable of retaining stored data without a power supply voltage applied thereto.
2. Description of the Related Art
Nonvolatile memories which have already been put to practical use or still being developed include flash EEPROMs employing a floating gate structure, FeRAMs employing a ferroelectric film, MRAMs employing a ferromagnetic film, etc.
FIGS. 14A through 14D are circuit diagrams showing a unit of storage (memory cell) of conventional memories. FIG. 14A illustrates a mask ROM, in which information indicative of either “0” or “1” stored at each memory cell is determined at the time of manufacturing. This information cannot be rewritten. The present invention relates to a nonvolatile memory in which information can be rewritten, and the mask ROM does not belong to this category.
FIG. 14B is a memory cell of a dynamic RAM (DRAM), and FIG. 14C is a memory cell of a static RAM (SRAM). These can retain stored information only when a power supply voltage is being applied. When the power supply is stopped, the stored information will be lost. The SRAM, in particular, has a circuit structure comprised of MOS transistors only, and can be implemented by use of a standard CMOS process used for logic LSIs without requiring any special process.
FIG. 14D is a ROM in which information is electrically rewritable. This ROM is conventionally referred to as an EEPROM. FIGS. 15A and 15B illustrate a basic structure of a special transistor constituting such ROM. As a notable feature, an electrode that is not electrically coupled to anywhere, referred to as a floating gate (FG), is provided between the original MOS transistor gate and the substrate.
A description will be given of the principle of the circuit operation of this EEPROM by referring to FIGS. 16A and 16B, FIGS. 17A and 17B, and FIGS. 18A and 18B as examples. In the case of an operation for writing information, as shown in FIGS. 16A and 16B, 6 V is applied to a bit line (BL), 12 V applied to a word line, and 0 V applied to a plate line (PL), for example. Due to the voltage applied to the word line, the gate receives a voltage of 12 V. Under this condition, the floating gate (FG) portion has a voltage applied thereto that ranges approximately from 1 V to 3 V, resulting in a channel being created as a path for electrons in the surface of the substrate (p-sub). The transistor is operating in the saturation region, and its channel is pinched off near the drain, so that a strong electric field is present in the proximity of the drain. Some of the electrons accelerated by this electric field jump into the floating gate. Because of this, the floating gate ends up retaining the electrons, resulting in the threshold voltage of the transistor being shifted toward a higher voltage as viewed from the gate node (word line). The injection of electrons into the floating gate is performed selectively and separately for each cell, thereby achieving the writing of information.
In the case of a read operation shown in FIGS. 17A and 17B, a difference in the threshold voltages shifted as described above is read as an electric current. 5 V is applied to the word line, 1 V applied to the bit line (BL), and (0V) applied to the plate line, for example. As a result, the transistors having floating gates connected to the word line have a read current (cell current) running therethrough. This cell current has an increased/decreased amount, depending on the high/low of the threshold voltage. The cell current is then amplified for the retrieval of information.
FIGS. 18A and 18B illustrate the principle of erasing information in a cell, i.e., removing electrons from the floating gate. The word line is fixed at 0 V, and the plate line is set to 12 V. A large potential difference thus develops between the plate and the floating gate, and the resultant electric field serves to remove electrons from the floating gate. This operation is performed with respect to all the memory cells that share the same plate line. The detail of the conventional memory operations described above is described in a large number of reference literatures (e.g., Tadayoshi Enomoto, “CMOS Integrated Circuit—From Entry to Practical Use”, Baifuukan, 1996, etc.).
For the EEPROMs that are conventional nonvolatile memories, there is a need to manufacture a transistor having the special construction, i.e., a transistor having a floating gate. As for FeRAMs and MRAMs, which achieve nonvolatile storage by use of ferroelectric material and ferromagnetic material, respectively, there is a need to form and process the film made of these materials. This is one of the big issues that need to be solved before practical use is achieved, and is also one of the factors that result in an increase in the manufacturing costs. There are memories, on the other hand, that store data by utilizing circuitry structure without requiring any special process. Such memories include SRAMs and DRAMs. SRAMs, in particular, do not require any special process in addition to the CMOS-type process, but have a drawback in that the stored contents are lost at power-off.
The issue to be solved is to provide a circuit that is CMOS-type process compatible and has a nonvolatile memory function.